The present invention relates to a semiconductor memory including a plurality of memory transistors having a diffusion interconnect layer structure and provided in the form of a matrix in a memory region and a logic transistor provided in a logic region, and a method for fabricating the semiconductor memory.
As an electrically writable nonvolatile memory, a semiconductor memory having a structure in which a diffusion interconnect layer also works as a source or a drain of a memory transistor (which structure is designated as a virtual ground structure) is conventionally known.
Recently, there are demands for further refinement, a higher degree of integration, higher performance and higher reliability of a semiconductor device, and a higher operation speed is required of also a semiconductor memory having the virtual ground structure.
Now, a conventional semiconductor memory including both memory transistors having the virtual ground structure and a logic transistor will be described with reference to FIGS. 19, and 20A through 20C. FIG. 20A is a cross-sectional view taken on line Za—Za of FIG. 19, FIG. 20B is a cross-sectional view taken on line Zb—Zb of FIG. 19 and FIG. 20C is a cross-sectional view taken on line Zc—Zc of FIG. 19.
As shown in FIGS. 19 and 20A through 20C, a first active region 11 corresponding to a memory region and a second active region 12 corresponding to a logic region isolated from each other by an isolation insulating film 13 are formed on a semiconductor substrate 10. A plurality of memory transistors are provided in the form of a matrix in the first active region 11 and a logic transistor is provided in the second active region 12.
In the first active region 11, a gate electrode 15 of each memory transistor is formed with a memory insulating film 14 sandwiched between the gate electrode 15 and the semiconductor substrate 10, and the memory insulating film 14 is composed of a multilayer structure including a lower gate insulating film 14a of a silicon oxide film, a capacitor film 14b of a silicon nitride film and an upper gate insulating film 14c of a silicon oxide film, and a sidewall insulating film 16 is formed on the side face of the gate electrode 15. The respective gate electrodes 15 of some memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, so that each common gate electrode 15 can correspond to a word line. On the other hand, impurity diffusion layers 17 working as the source and drain regions of some memory transistors arranged along the bit line direction out of the plural memory transistors are formed as a common impurity diffusion layer extending along the bit line direction, so that each common impurity diffusion layer 17 can correspond to a bit line. The plural memory transistors are covered with a memory region protection insulating film 18. In FIG. 19, however, the memory region protection insulating film 18 is omitted for convenience of the drawing.
In the second active region 12, a gate electrode 22 of the logic transistor is formed with a logic insulating film 21 of a silicon oxide film sandwiched between the gate electrode 22 and the semiconductor substrate 10, and a sidewall insulating film 23 is formed on the side face of the gate electrode 22. Also in the second active region 12, impurity diffusion layers 24 working as the source and drain regions are formed, and a silicide layer 25 is formed on the gate electrode 22 and the impurity diffusion layers 24.
Now, a method for fabricating the conventional semiconductor memory will be described with reference to FIGS. 21A through 21C, 22A through 22C, 23A through 23C and 24A through 24C. FIGS. 21A, 22A, 23A and 24A are cross-sectional views taken on line Za—Za of FIG. 19, FIGS. 21B, 22B, 23B and 24B are cross-sectional views taken on line Zb—Zb of FIGS. 19 and 21C, 22C, 23C and 24C are cross-sectional views taken on line Zc—Zc of FIG. 19.
First, as shown in FIGS. 21A through 21C, an isolation insulating film 13 of a silicon oxide film is formed in a surface portion of a semiconductor substrate 10, so as to form a first active region 11 corresponding to a memory region and a second active region 12 corresponding to a logic region. Thereafter, impurity ions such as arsenic ions are implanted into predetermined portions of the first active region 11 and annealing is then carried out, so as to form impurity diffusion layers 17 working as the source and drain regions of memory transistors and extending along the bit line direction.
Next, as shown in FIGS. 22A through 22C, in the first active region 11 and the second active region 12, a lower silicon oxide film is formed through thermal oxidation, and thereafter, an intermediate silicon nitride film and an upper silicon oxide film are deposited by low pressure CVD in the first active region 11. Then, a polysilicon film is deposited by the low pressure CVD in the first active region 11 and the second active region 12. Subsequently, the polysilicon film, the upper silicon oxide film, the intermediate silicon nitride film and the lower silicon oxide film are patterned in the first active region 11, so as to form a gate electrode 15 of each memory transistor from the polysilicon film, an upper gate insulating film 14c from the upper silicon oxide film, a capacitor film 14b from the intermediate silicon nitride film and a lower gate insulating film 14a from the lower silicon oxide film. In this manner, a memory gate insulating film 14 composed of a multilayer structure including the upper gate insulating film 14c, the capacitor film 14b and the lower gate insulating film 14a is formed below the gate electrode 15 of each memory transistor. On the other hand, in the second active region 12, the polysilicon film and the lower silicon oxide film are patterned, so as to form a gate electrode 22 of a logic transistor from the polysilicon film and a logic gate insulating film 21 from the lower silicon oxide film.
Next, in the first active region 11 and the second active region 12, a silicon oxide film is deposited by the low pressure CVD and the silicon oxide film is etched back, so as to form a sidewall insulating film 16 on the side face of the gate electrode 14 of each memory transistor and a sidewall insulating film 23 on the side face of the gate electrode 22 of the logic transistor. Then, in the second active region 12, impurity ions such as arsenic ions are implanted by using the gate electrode 22 and the sidewall insulating film 23 of the logic transistor as a mask and annealing is then carried out, so as to form impurity diffusion layers 24 working as source and drain regions.
Subsequently, as shown in FIGS. 23A through 23C, in the first active region 11 and the second active region 12, a silicon oxide film is deposited by the low pressure CVD, and a resist pattern 26 having an opening in the second active region 12 is formed on the silicon oxide film. Thereafter, the silicon oxide film is etched by using the resist pattern 26 as a mask, so as to form a memory region protection insulating film 18 for covering the first active region 11.
Then, as shown in FIGS. 24A through 24C, the resist pattern 26 is removed, and a silicide layer 25 is formed on the gate electrode 22 and the impurity diffusion layers 24 of the logic transistor by salicide technique. Thus, the conventional semiconductor memory is completed.
Although procedures for forming metal interconnects, forming a protection film and forming bonding pads are carried out thereafter, these procedures are not described herein because they are known.
Since the operation speed of a semiconductor memory is required to be increased, a silicide layer is desired to be formed on the gate electrode 15 of each memory transistor.
In order to form a suicide layer on the gate electrode 15 of the memory transistor, it is necessary to practice the salicide technique without forming the memory region protection insulating film 18 in the first active region 11. However, when the salicide technique is thus practiced, the silicide layer is unavoidably formed on the impurity diffusion layers 17 of the memory transistors, which causes a problem that the source and drain regions of a plurality of memory transistors arranged along the bit line direction are short-circuited.